Eugene Hutorny

Vision in examples

The following table illustrates my vision on e#, giving examples in MP ASM and what could be their equivalents in e# application and corresponding to them parts of device definition (in a hypothetical syntax).




MP ASM
    
e# application
  
e# device definition  


addwf myfile,W
WREG += myfile
class WREG … instruction '+='(file);


addwf myfile,F
myfile += WREG
class file … instruction '+='(WREG);


clrf myfile
myfile = 0
class file … instruction '='(const 0..0);


clrw 
WREG = 0
class WREG … instruction '='(const 0..0);


decf myfile,W
WREG = myfile--
class WREG … instruction '='(file)'--';


decf myfile,F
myfile--
class file … instruction '—';


decfsz myfile,W

            goto myloop
if(WREG = myfile--) goto    myloop
class WREG … instruction if '('(this)'='(file)'--'    ')' (instruction);


decfsz myfile,F
if(myfile--)
class file … instruction if '(' (this)'-–' ')'(instruction);


movf myfile, W
WREG = myfile
 


testf myfile, F
myfile.test
class file … instruction '.' test;


movwf myfile
myfile = WREG
class file … instruction '='(WREG);


 


bsf myfile,mybit
myfile[mybit] = 1

class file … operator [(const 0..7)] : bit;

            class bit … instruction '='(const 0..1)



bcf myfile,mybit
myfile[mybit] = 0


btfss myfile, mybit
if(~myfile[mybit])
class bit … 

            instruction if '(' '~'(this)')' (instruction);


btfsc myfile, mybit
if(myfile[mybit])
class bit … 

            instruction if '(' (this) ')'(instruction);


 
 
 


addlw myliteral
WREG += myliteral
class WREG … instruction '+='(const 0..FFh);


movlw myliteral
WREG = myliteral
class WREG … instruction '='(const 0..FFh);


 
 
 


bcf INTCON,T0IF
TMR0.IF = 0
class TMR0 … alias IF is INTCON.TMR0IF;


bsf INTCON,T0IE
TMR0.IE = 1
class TMR0 … alias IE is INTCON.TMR0IE;


  


mylbl:

      …

      goto mylbl
codelabel mylbl;

      …

      goto mylbl;
architecture mcu …

            instruction goto(codelabel);


mysub: 

        ; do something

        return

      call mysub
sub mysub;

      //do something 

      return; end sub;

      mysub;

architecture mcu …

  instruction return;

      class sub extends codelabel …

            instruction MCU.call default; 



 


macro mymacro myparam

      endm
inline mymacro(afile : file)

            end inline mymacro;

MP ASM	e# application	e# device definition
addwf myfile,W	WREG += myfile	class WREG … instruction '+='(file);
addwf myfile,F	myfile += WREG	class file … instruction '+='(WREG);
clrf myfile	myfile = 0	class file … instruction '='(const 0..0);
clrw	WREG = 0	class WREG … instruction '='(const 0..0);
decf myfile,W	WREG = myfile--	class WREG … instruction '='(file)'--';
decf myfile,F	myfile--	class file … instruction '—';
decfsz myfile,W goto myloop	if(WREG = myfile--) goto myloop	class WREG … instruction if '('(this)'='(file)'`--`' ')' (instruction);
decfsz myfile,F	if(myfile--)	class file … instruction if '(' (this)'-–' ')'(instruction);
movf myfile, W	WREG = myfile
testf myfile, F	myfile.test	class file … instruction '.' test;
movwf myfile	myfile = WREG	class file … instruction '='(WREG);

bsf myfile,mybit	myfile[mybit] = 1	class file … operator [(const 0..7)] : bit; class bit … instruction '='(const 0..1)
bcf myfile,mybit	myfile[mybit] = 0
btfss myfile, mybit	if(~myfile[mybit])	class bit … instruction if '(' '~'(this)')' (instruction);
btfsc myfile, mybit	if(myfile[mybit])	class bit … instruction if '(' (this) ')'(instruction);

addlw myliteral	WREG += myliteral	class WREG … instruction '+='(const 0..FFh);
movlw myliteral	WREG = myliteral	class WREG … instruction '='(const 0..FFh);

bcf INTCON,T0IF	TMR0.IF = 0	class TMR0 … alias IF is INTCON.TMR0IF;
bsf INTCON,T0IE	TMR0.IE = 1	class TMR0 … alias IE is INTCON.TMR0IE;

mylbl: … goto mylbl	codelabel mylbl; … goto mylbl;	architecture mcu … instruction goto(codelabel);
mysub: ; do something return call mysub	sub mysub; //do something return; end sub; mysub;	architecture mcu … instruction return; class sub extends codelabel … instruction MCU.call default;

macro mymacro myparam endm	inline mymacro(afile : file) end inline mymacro;

Hypothetical example of a library

`library basicflowcontrol for architecture mcu; inline while '(' (file f) > (const c 0..FFh) ')' (codeobjects) 'end' 'while' violates ACCU; begin codelabel l1; ACCU = a; ACCU -= f; if( STATUS.Z ) goto l2; codeobjects; goto codelable l1; codelabel l2; end inline; end library;`		This is a hypothetical example of a library implementing high-level flow control statements (while(A>C) ) for a generic (abstract) MCU. It uses only three features of MCU – (1) working register (accumulator), (2) Z flag of the STATUS register and instruction goto. The abstract MCU provide no knowledge on instruction format, register location and so on. It only establishes a lowest common subset of MCU’s facilities, which can be used to express program logic.
`application``myapplication for PIC16F84; uses basicflowcontrol; begin FSR = 7Fh; while( FSR > 20h ) INDF = 0; FSR--; end while; … end application;`		This example illustrates how a library defined in the previous example is used in an application. The statement while, defined in the library, will be instantiated with the body, defined in the library and instructions used in the library will be instantiated with actual PIC16F84 instruction (assumption behind this – PIC16F84 is a descendant of a generic MCU)

Hypothetical examples of other activities

sub delay10us { sim: time t = getTime(); /* simulation-time statements */ } W = 10us / CycleDuration; codelabel l; W += -1; if(~STATUS.Z) goto l; { sim: if( t – getTime() ) != 10 us then error('delay10us is malfunctioning'); } end sub

This example illustrates use of simulation-time statements for validating a delay routine. At the first line denoted with ‘{ sim:‘ current simulation time is stored in the variable. In the second simulation time the code calculates the simulated delay time and validates it against expected 10 us and reports a error if mismatch detected.

Pages: 1 2 3 4 All Pages

Concept of a new PL for embedded applications

Vision in examples

Hypothetical example of a library

Hypothetical examples of other activities

One Comment